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DS1023 8bit programmable timing element DS1023 062498 1/17 features ? step sizes of 0.25, 0.5 ns, 1 ns, 2 ns, 5 ns ? onchip reference delay ? configurable as delay line, pulse width modulator, or freerunning oscillator ? can delay clocks by a full period or more ? guaranteed monotonicity ? parallel or serial programming ? single 5v supply ? 16pin dip or soic package pin assignment 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DS1023 300mil dip v cc out/out p /s p7 p6 ms p5 ref/pwm in le q/p0 clk/p1 d/p2 p3 p4 gnd DS1023s 300mil soic pin descriptions in input p0/q parallel input p0 (parallel mode) serial data output (serial mode) p1/clk parallel input p1 (parallel mode) serial input clock (serial mode) p2/d parallel input p2 (parallel mode) serial data input (serial mode) p3 p7 remaining parallel inputs gnd ground out/out output ref/pwm reference or pwm output p /s parallel / serial programming select ms output mode select le input latch enable v cc supply voltage description the DS1023 is an 8bit programmable delay line simi- lar in function to the ds1020/ds1021. additional features have been added to extend the range of applications: the internal delay line architecture has been revised to allow clock signals to be delayed by up to a full period or more. combined with an onchip reference delay (to offset the inherent or astep zeroo delay of the device) clock phase can now be varied over the full 0360 degree range. onchip gating is provided to allow the device to provide a pulse width modulated output, triggered by the input with duration set by the programmed value. alternatively the output signal may be inverted on chip, allowing the device to perform as a freerunning oscilla- tor if the output is (externally) connected to the input. programming the device programming is identical to the ds1020/ds1021. note however that the serial clock and data pins are shared with three of the parallel input pins.
DS1023 062498 2/17 the p /s pin controls the same function as amode selecto on the ds1020/ds1021 (but with reversed polarity). a low logic level on this pin enables the parallel program- ming mode. le must be at a high logic level to alter the programmed value, when le is taken low the data is latched internally and the parallel data inputs may be altered without affecting the programmed value. this is useful for multiplexed bus applications. for hardwired applications le should be tied to a high logic level. when p /s is high serial programming is enabled. le must be held high to enable loading or reading of the internal register, during which time the delay is deter- mined by the previously programmed value. data is clocked in msb to lsb order on the rising edge of the clk input. data transfer ends and the new value is acti- vated when le is taken low. parallel mode (p /s = 0) in the parallel programming mode, the output of the DS1023 will reproduce the logic state of the input after a delay determined by the state of the eight program input pins p0 p7. the parallel inputs can be programmed using dc levels or computergenerated data. for infre- quent modification of the delay value, jumpers may be used to connect the input pins to v cc or ground. for applications requiring frequent timing adjustment, dip switches may be used. the latch enable pin (le) must be at a logic 1 in hardwired implementations. maximum flexibility is obtained when the eight parallel programming bits are set using computergenerated data. when the data setup (t dse ) and data hold (t dhe ) requirements are observed, the enable pin can be used to latch data supplied on an 8bit bus. latch enable must be held at a logic 1 if it is not used to latch the data. after each change in delay value, a settling time (t edv or t pdv ) is required before input logic levels are accurately delayed. serial mode (p /s = 1) in the serial programming mode, the output of the DS1023 will reproduce the logic state of the input after a delay time determined by an 8bit value clocked into se- rial port d. while observing data setup (t dsc ) and data hold (t dhc ) requirements, timing data is loaded in msb tolsb order by the rising edge of the serial clock (clk). the latch enable pin (le) must be at a logic 1 to load or read the internal 8bit input register, during which time the delay is determined by the last value acti- vated. data transfer ends and the new delay value is ac- tivated when latch enable (le) returns to a logic 0. after each change, a settling time (t edv ) is required before the delay is accurate. as timing values are shifted into the serial data input (d), the previous contents of the 8bit input register are shifted out of the serial output pin (q) in msbtolsb order. by connecting the serial output of one DS1023 to the serial input of a second DS1023, multiple devices can be daisychained (cascaded) for programming pur- poses (figure 1). the total number of serial bits must be eight times the number of units daisychained and each group of 8 bits must be sent in msbtolsb order. applications can read the setting of the DS1023 delay line by connecting the serial output pin (q) to the serial input (d) through a resistor with a value of 1k to 10k ohms (figure 2). since the read process is destructive, the resistor restores the value read and provides isola- tion when writing to the device. the resistor must con- nect the serial output (q) of the last device to the serial input (d) of the first device of a daisychain (figure 1). for serial readout with automatic restoration through a resistor, the device used to write serial data must go to a high impedance state. to initiate a serial read, latch enable (le) is taken to a logic 1 while serial clock (clk) is at a logic 0. after a waiting time (t eqv ), bit 7 (msb) appears on the serial output (q). on the first rising (0 --> 1) transition of the serial clock (clk), bit 7 (msb) is rewritten and bit 6 ap- pears on the output after a time t cqv . to restore the in- put register to its original state, this clocking process must be repeated eight times. in the case of a daisy- chain, the process must be repeated eight times per package. if the value read is restored before latch enable (le) is returned to logic 0, no settling time (t edv ) is required and the programmed delay remains un- changed. since the DS1023 is a cmos design, unused input pins (p3 p7) must be connected to welldefined logic lev- els; they must not be allowed to float. serial output q/p0 should be allowed to float if unused.
DS1023 062498 3/17 cascading multiple devices (daisy chain) figure 1 DS1023 dq to reading device from writing device with floating output state 1k to 10k optional feedback resistor DS1023 dq dq DS1023 serial readout figure 2 DS1023 dq to reading device from writing device with floating output state 1k to 10k feedback resistor reference delay in all delay lines there is an inherent, or astep zeroo, delay caused by the propagation delay through the input and output buffers. in this device the step zero delay can be quite large compared to the delay step size. to sim- plify system design a reference delay has been included on chip which may be used to compensate for the step zero delay. in practice this means that if the device is supplied with a clock, for example, the minimum pro- grammed output delay is effectively zero with respect to the reference delay. for highest accuracy it is strongly recommended that the reference delay is used. varia- tions in input voltage levels and transition times can sig- nificantly alter the measured delay from input to output. this effect is totally removed if the reference delay out- put is used. furthermore, adverse effects on step zero delay caused by process temperature coefficients are also cancelled out. DS1023 in ref out in ref out t wi t ref t d0 t dmax t dmax
DS1023 062498 4/17 input pulse duration the internal architecture of the DS1023 allows the out- put delay time to be considerably longer than the input pulse width (see ac specifications). this feature is use- ful in many applications, in particular clock phase con- trol where delays up to and beyond one full clock period can be achieved. mode select figure 3 ms = 0 in ref out t ref t d the output is the same polarity as the input, delayed according to the programmed values. the ref output also is the same polarity as the input, delayed by an amount approximately equal to the step zero value of the programmed delay. with respect to the ref signal the output signal can be varied in phase from 0 360 degrees, or more. ms = 1 figure 4 in pwm out t d t ref depending on how the user configures the device two different modes are possible. by externally connecting the output (the output is inverted with respect to the input when ms=1) to the input a freerunning oscillator will be produced, with frequency varying according to the programmed delay value. alternatively an input pulse can be applied to initiate a pulse at the pwm out- put, with a duration according to the programmed delay time. the output pin meanwhile will produce a delayed and inverted representation of the input waveform. pwm mode in pwm mode the input and output signals are gated to produce a pulse width determined by the programmed value. the output pulse is delayed from the input's rising edge by an amount approximately equal to the refer- ence delay of the device. by using the onchip refer- ence delay, output pulse widths can be obtained from (nearly) zero to the full delay range of the device. the minimum output pulse width is limited by the response of the device output stage (see ac specifications), if val- ues less than the minimum are programmed the output voltage swing will initially degrade until ultimately no dis- cernable output pulse is produced. the input trigger pulse can be shorter than the output pulse width, and is limited only by the input pulse duration specification.
DS1023 062498 5/17 functional block diagram figure 5 reference delay programmable delay (see detail) ref/pwm out/out ms output mode control 8bit latch 8bit input register p0/ q p1/ clk p2/ d p3 p7 le p /s in delay line detail (conceptual) DS1023200, DS1023500 figure 6 input output t d t d t d t d 256 256line decoder from 8bit latch fixed delay 255element array DS1023200 t d = 2 ns DS1023500 t d = 5 ns
DS1023 062498 6/17 delay line detail (conceptual) DS102325, DS102350, DS1023100 figure 7 input output t d t d t d t d 32, 64, 128 128, 64, 32line decoder from 8bit latch fixed delay array (31, 63, 127 elements) 1, 2, 3bit subdac t d = 2 ns 1, 2, 3 lsb's device option DS102325 DS102350 DS1023100 subdac (bits) 3 2 1 fixed elements 32 64 128 step size (ns) 0.25 0.50 1.00 part number table table 1 delays ranges and tolerance (all times measured in ns) part number step size max. delay time (1)/ max. output pulse width (2) maximum deviation (3) maximum i/p freq minimum i/p pulse width DS1023025 0.25 63.75 1 25 mhz 20 DS1023050 0.50 127.5 2 25 mhz 20 DS1023100 1.0 255 4 25 mhz 20 DS1023200 2.0 510 8 25 mhz 20 DS1023500 5.0 1275 20 10 mhz 50 1. in anormalo mode (ms=0). measured with respect to ref output. the minimum delay time is zero (or less, by up to two steps) 2. in pwm mode (ms=1). the minimum output pulse width for reliable operation is 5 ns, programmed values less than this may produce reduced output voltage levels or no output at all. 3. this is the deviation from a straight line drawn between the step zero value and the maximum programmed delay time.
DS1023 062498 7/17 oscillator configuration table 2 part number step size (4) minimum o/p frequency (5) maximum o/p frequency (5) DS1023025 0.5 6.6 mhz 22 mhz DS1023050 1.0 3.6 mhz 22 mhz DS1023100 2.0 1.9 mhz 22 mhz DS1023200 4.0 0.98 mhz 22 mhz DS1023500 10.0 0.4 mhz 22 mhz 4. step size in output period (in ns). 5. maximum output frequency depends on the actual step zero delay value, worst case values are shown in the table. the output period is given by: 2 * t d where: t d = absolute delay value.
DS1023 062498 8/17 dallas semiconductor test circuit figure 8 z o 50 pulse generator time interval counter z o 50 device under test in out DS1023 computer 74f04 test setup description figure 8 illustrates the hardware configuration used for measuring the timing parameters of the DS1023. the input waveform is produced by a precision pulse gener- ator under software control. time delays are measured by a time interval counter (20 ps resolution) connected to the output. the DS1023 serial and parallel ports are controlled by interfaces to a central computer. all mea- surements are fully automated with each instrument controlled by the computer over an ieee 488 bus. test conditions input: ambient temperature: 25 c 3 c supply voltage (v cc ): 5.0v 0.1v input pulse: high = 3.0v 0.1v low = 0.0v 0.1v source impedance: 50 ohms max. rise and fall time: 3.0 ns max. (measured between 0.6v and 2.4v) pulse width: 500 ns period: 1 m s note: above conditions are for test only and do not restrict the operation of the device un- der other data sheet conditions. output: output is loaded with a 74f04. delay is measured be- tween the 1.5v level of the rising edge of the input signal and the 1.5v level of the corresponding edge of the out- put.
DS1023 062498 9/17 absolute maximum ratings* voltage on any pin 1.0v to +7.0v operating temperature range 0 c to 70 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds short circuit output current 50 ma for 1 second * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (0 c to 70 c; v cc = 5v 5%) parameter symbol min typ max units notes supply voltage v cc 4.75 5 5.25 v high level input voltage v ih 2 v cc +0.5 v low level input voltage v il 0.5 0.8 v input leakage current (0 DS1023 062498 10/17 parameter notes units max typ min symbol parallel input to delay valid t pdv 500 ns parallel input to delay invalid t pdx 0 ns le to delay valid t edv 500 ns le to delay invalid t edx 0 ns power up time t pu 100 ms timing diagram: silicon delay line figure 9 1.5v 1.5v 1.5v 1.5v 1.5v in t fall t rise 80% 20% out t wi t wi period t dr t df
DS1023 062498 11/17 ac electrical characteristics DS1023025 delay specifications (t a = 0 c to 70 c; v cc = 5v 5%) parameter symbol min typ max units notes step zero delay absolute wrt ref t d0 t dref0 2 16.5 1.5 22 0 ns ns 1, 13 2, 14 reference delay t ref 18 22 ns 3, 13 delay step size t step 0 0.25 0.75 ns 4 maximum delay absolute wrt ref t dmax t dref 75 60 80 63.5 89 67.5 ns ns 5, 13 6, 14 delay matching, rising edge to falling edge 1 +1 ns 15 integral nonlinearity (deviation from straight line) t err 1 0 +1 ns 7 out delta delay t inv0 0 1 2 ns 8 in high to pwm high t pwm0 16.5 22 ns 9, 13 minimum pwm output pulse width t pwm 5 ns 10 minimum input pulse width t wi 20 ns 11 minimum input period 40 ns 12 ac electrical characteristics DS1023050 delay specifications (t a = 0 c to 70 c; v cc = 5v 5%) parameter symbol min typ max units notes step zero delay absolute wrt ref t d0 t dref0 2 16.5 1.5 22 0 ns ns 1, 13 2, 14 reference delay t ref 18 22 ns 3, 13 delay step size t step 0 0.5 1.5 ns 4 maximum delay absolute wrt ref t dmax t dref 139 123 144 127.5 154 132 ns ns 5, 13 6, 14 delay matching, rising edge to falling edge 1 +1 ns 15 integral nonlinearity (deviation from straight line) t err 2 0 +2 ns 7 out delta delay t inv0 0 1 2 ns 8 in high to pwm high t pwm0 16.5 22 ns 9, 13 minimum pwm output pulse width t pwm 5 ns 10 minimum input pulse width t wi 20 ns 11 minimum input period 40 ns 12
DS1023 062498 12/17 ac electrical characteristics DS1023100 delay specifications (t a = 0 c 70 c; v cc = 5v 5%) parameter symbol min typ max units notes step zero delay absolute wrt ref t d0 t dref0 2 16.5 1.5 22 0 ns ns 1, 13 2, 14 reference delay t ref 18 22 ns 3, 13 delay step size t step 0 1 1.5 ns 4 maximum delay absolute wrt ref t dmax t dref 262 247 272 255 285 263 ns ns 5, 13 6, 14 delay matching, rising edge to falling edge 1 +1 ns 15 integral nonlinearity (deviation from straight line) t err 4 0 +4 ns 7 out delta delay t inv0 0 1 2 ns 8 in high to pwm high t pwm0 16.5 22 ns 9, 13 minimum pwm output pulse width t pwm 5 ns 10 minimum input pulse width t wi 20 ns 11 minimum input period 40 ns 12 ac electrical characteristics DS1023200 delay specifications (t a = 0 c 70 c; v cc = 5v 5%) parameter symbol min typ max units notes step zero delay absolute wrt ref t d0 t dref0 2 16.5 1.5 22 0 ns ns 1, 13 2, 14 reference delay t ref 18 22 ns 3, 13 delay step size t step 1.8 2 2.2 ns maximum delay absolute wrt ref t dmax t dref 509 494 527 510 548 526 ns ns 5, 13 6, 14 delay matching, rising edge to falling edge 1 +1 ns 15 integral nonlinearity (deviation from straight line) t err 8 0 +8 ns 7 out delta delay t inv0 0 1 2 ns 8 in high to pwm high t pwm0 16.5 22 ns 9, 13 minimum pwm output pulse width t pwm 5 ns 10 minimum input pulse width t wi 20 ns 11 minimum input period 40 ns 12
DS1023 062498 13/17 ac electrical characteristics DS1023500 delay specifications (t a = 0 c 70 c; v cc = 5v 5%) parameter symbol min typ max units notes step zero delay absolute wrt ref t d0 t dref0 2 16.5 1.5 22 0 ns ns 1, 13 2, 14 reference delay t ref 18 22 ns 3, 13 delay step size t step 4.5 5 5.5 ns maximum delay absolute wrt ref t dmax t dref 1250 1235 1292 1275 1337 1315 ns ns 5, 13 6, 14 delay matching, rising edge to falling edge 1 +1 ns 15 integral nonlinearity (deviation from straight line) t err 20 0 +20 ns 7 out delta delay t inv0 0 1 2 ns 8 in high to pwm high t pwm0 16.5 22 ns 9, 13 minimum pwm output pulse width t pwm 5 ns 10 minimum input pulse width t wi 50 ns 11 minimum input period 100 ns 12 notes: 1. delay from input to output with a programmed delay value of zero. 2. this is the relative delay between ref and out. the device is trimmed such that when programmed to zero delay the ref output will always appear before the out output. this parameter is numerically equal to t d0 t ref . (see figure 15) 3. the reference delay is closely matched to the step zero delay to allow relative timings down to zero or less. 4. this is the worst case condition when the subdac switches from its maximum to minimum value. all other steps are 0.5 lsb. this comment does not apply to 200 and 500 devices which do not use a subdac. (see figure 14) 5. this is the actual measured delay from in to out. this parameter will exhibit greater temperature variation than the relative delay parameter. 6. this is the actual measured delay with respect to the ref output. this parameter more closely reflects the pro- grammed delay value than the absolute delay parameter. (see figure 15) 7. this is the maximum deviation from a straight line response drawn between the step zero delay and the maximum programmed delay. therefore it is indicative of the maximum error in the measured delay versus the programmed delay with respect to the ref output. the absolute delay measurement from in to out will in addition have an offset error equal to the step zero delay and its tolerance. (see figure 13) 8. change in delay value when the inverted output is selected instead of the normal, noninverting, output. 9. in pwm mode the delay between the rising edge of the input and the rising edge of the output.
DS1023 062498 14/17 10. the minimum value for which the pwm pulse width should be programmed. narrower pulse widths may be pro- grammed but output levels may be impaired and ultimately no output pulse will be produced. 11. this is the minimum allowable interval between transitions on the input to assure accurate device operation. this parameter may be violated but timing accuracy may be impaired and ultimately very narrow pulse widths will result in no output from the device. 12. when a 50% duty cycle input clock is used this defines the highest usable clock frequency. when asymmetri- cal clock inputs are used the maximum usable clock frequency must be reduced to conform to the minimum input pulse width requirement 13. measured from rising edge of the input to the rising edge of the output (t dr ). 14. from rising edge to rising edge. 15. this is the difference in measured delay between rising edge (input to output), t dr and falling edges (input to output), t df . terminology period: the time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t wi (pulse width): the elapsed time on the pulse be- tween the 1.5v point on the leading edge and the 1.5v point on the trailing edge, or the 1.5v point on the trailing edge and the 1.5v point on the leading edge. t rise (input rise time): the elapsed time between the 20% and the 80% point on the leading edge of the input pulse. t fall (input fall time): the elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. t d (time delay): the elapsed time between the 1.5v point on the edge of an input pulse and the 1.5v point on the corresponding edge of the output pulse. timing diagram: nonlatched parallel mode (p /s = 0, le = 1) figure 10 parallel inputs p0p7 previous value new value previous value new value delay time t pdx t pdv
DS1023 062498 15/17 timing diagram: latched parallel mode (p /s = 0) figure 11 previous value new value t edx t edv new value t dse t dhe t ew enable (le) parallel inputs p0p7 delay time timing diagram: serial mode (p /s = 1) figure 12 t ew enable t es (le) clock (clk) serial input (d) serial input (q) delay time previous value new value old bit 0 old bit 6 old bit 7 new bit 7 new bit 6 new bit 0 t cw t cw t eh t dsc t dhc t egv t cqv t cqx t eqz t edv t edx
DS1023 062498 16/17 delay vs programmed value figure 13 delay time t dmax t d0 0 255 see detailed response characteristics t err actual response (exaggerated) ideal response step detailed response characteristics figure 14 delay (ns) DS1023025 ideal response subdac value (lsb's) 012 34 56 7 0 delay (ns) 2(n+1) DS1023050 ideal response 2n subdac value (lsb's) 01230 delay (ns) ideal response n delay (ns) DS1023100 ideal response 2n subdac value (lsb's) 010 2(n+1) t step t step t step DS1023200 2(n+1) n+1 n+2 5(n+2) 5(n+1) 5n 2n 2(n+1) 2n 2(n+2) DS1023500 step number (no subdac)
DS1023 062498 17/17 delay parameters figure 15 t dmax t d0 0 255 t dref step delay t dref0 t ref notes: 1. the device is trimmed such that t dref = 255 * (nominal step size). 2. since t do is trimmed to be less than t ref , the actual step size will be slightly above the nominal value. 3. consequently the range of absolute delay values (t dmax t do ) will also exceed the nominal range by an amount equal to t dref0 .

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